CS4341-CZZ【PDF 15/34 页】IC DAC STER 24BIT 96KHZ 16TSSOP

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CS4341

DS298F5

4.9.3a

IC Write

To write to the device, follow the procedure below while adhering to the control port Switching

Specifications in section 6.

Initiate a START condition to the IC bus followed by the address byte. The upper 6 bits must

be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0.

The eighth bit of the address byte is the R/W bit.

Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP.

This byte points to the register to be written.

Wait for an acknowledge (ACK) from the part, then write the desired data to the register point-

ed to by the MAP.

If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired

registers are written, then initiate a STOP condition to the bus.

If the INCR bit is set to 0 and further IC writes to other registers are desired, it is necessary to

repeat the procedure detailed from step 1. If no further writes to other registers are desired,

initiate a STOP condition to the bus.

4.9.3b

IC Read

To read from the device, follow the procedure below while adhering to the control port Switching

Specifications. During this operation it is first necessary to write to the device, specifying the ap-

propriate register through the MAP.

After writing to the MAP (see section 4.9.3a), initiate a repeated START condition to the IC

bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must

match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte

is the R/W bit.

Signal the end of the address byte by not issuing an acknowledge. The device will then trans-

mit the contents of the register pointed to by the MAP. The MAP will contain the address of the

last register written to the MAP.

If the INCR bit is set to 1, the device will continue to transmit the contents of successive reg-

isters. Continue providing a clock but do not issue an ACK on the bytes clocked out of the de-

vice. After all the desired registers are read, initiate a STOP condition to the bus.

If the INCR bit is set to 0 and further IC reads from other registers are desired, it is necessary

to repeat the procedure detailed from step 1. If no further reads from other registers are de-

sired, initiate a STOP condition to the bus.

SD A

SC L

001000

AD0

Sta rt

ACK

MAP

1-8

ACK

DATA

1-8

ACK

Stop

Figure 22. IC Write

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